Samsung Electronics Co. Ltd. said today it has managed to squeeze an extra four layers onto its current eight-layer High Bandwidth Memory-2 products.

High Bandwidth Memory-2 is a kind of memory interface used in 3D-stacked dynamic random access memory for graphics processing units, computer servers, high-performance computing and networking.

The new packaging technology, called 12-layer 3D-Through Silicon Via, relies on the pinpoint alignment of 60,000 TSV holes, through which bond wires are threaded. Each of those holes is around a 20th of the thickness of a human hair, Samsung said.

The 12-layer package has the same dimensions as Samsung’s current eight-layer memory chip package at 720 micrometers thick, but it allows more storage to be packed into the same space. At the same time, the new package also increases performance and boosts power consumption as it has shorter data transmission times.

Samsung said the new technology will enable it to start mass producing a 24-gigabyte High Bandwidth Memory chip that offers three times the capacity of its current 8GB memory. The new product should be useful in artificial intelligence and high-performance computing applications, the company said.

“Packaging technology that secures all of the intricacies of ultra-performance memory is becoming tremendously important, with the wide variety of new-age applications, such as AI and HPC,” Hong-Joo Baek, Samsung’s executive vice president of Test & System Package, said in a statement. “As Moore’s law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical. We want to be at the forefront of this state-of-the-art chip packaging technology.”

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