Cadence Design Systems Inc. today launched a new artificial intelligence platform, Cerebrus Intelligent Chip Explorer, that it says can improve the productivity of semiconductor engineers and help them develop faster chips. 

Publicly traded Cadence is one of the world’s top makers of chip design software. Its software is used by Nvidia Corp., Advanced Micro Devices Inc. and many other major players in the semiconductor market to develop new products. The company posted revenue of $2.68 billion in its 2020 fiscal year. 

Chip design teams need software tools such as those sold by Cadence to help them with semiconductor development because modern processors contain as many as billions of transistors. It’s impossible manually to determine the optimal way to build, configure and link together so many transistors. Cadence’s software automates a big portion of the calculations involved in developing a chip so engineers can save time and focus on the most important aspects of a project.

The company’s newly debuted Cerebrus platform uses machine learning to automate even more aspects of engineers’ work.

One phase of chip projects that Cerebrus promises to speed up is what’s known in the semiconductor industry as the register-transfer level development process. Engineers start building a new chip by creating an abstract representation of how data will move through the chip and what computations should be performed on the data by transistors. This abstract representation is referred to as the register-transfer level.

Most of the resources that go into the process are spent not on creating the initial version of a chip’s abstract representation but rather on fine-tuning it. Engineers create a prototype design, measure its performance and then fine-tune a few features to improve performance. They repeat this process many times until arriving at a chip design that meets the project’s performance and power efficiency goals.

Cerberus uses an artificial intelligence approach called reinforcement learning to automate parts of the workflow. In reinforcement learning, an AI is given a task with few specific instructions on how to accomplish it. The AI receives virtual rewards when it gets closer to completing the task and virtual penalties when it makes an error. By analyzing the occasions when it receives rewards, the AI figures out the optimal way to reach the objective.

Cadence has applied this concept to chip design. Chip engineers can provide Cerberus with the abstract register-transfer level representation of a chip, then instruct the software to refine the design until a certain combination of chip performance and power efficiency is achieved. Cerberus performs the task using reinforcement learning algorithms. 

When the algorithms move closer to the specified performance and efficiency objective, they receive a virtual reward that signals they should continue in the same direction. When the algorithms make a design change that has the opposite effect, a virtual penalty is given. That allows Cerebrus to identify useful design variations and incorporate them into the chip’s abstract representation.

Cerebrus also streamlines chip development at a lower level of abstraction. Once a chip design team creates the register-transfer level representation of the chip, the next step is implementing the representation in hardware. That involves creating a highly detailed blueprint of how transistors should be arranged on the chip. Engineers must create the blueprint while taking into account complex microscopic phenomena, such as fluctuations in the voltage of the electricity that travels between the individual circuits.

Among the hardware-level tasks Cerebrus can help partially automate is floorplan creation. That’s the process of figuring out the optimal placement of circuits on a chip. One early user of Cerebrus’ floorplan optimization feature is Renesas Electronics Corp., one of the auto sector’s main semiconductor suppliers, which used the software to improve performance of a recently developed chip by more than 10%.

“Cerebrus, with its innovative ML capabilities, and the Cadence RTL-to-signoff tools have provided automated flow optimization and floorplan exploration, improving design performance by more than 10%,” said Renesas executive Satoshi Shibatani. “Following this success, the new approach will be adopted in the development of our latest design projects.”

Renesas is among the more than dozen early customers that have adopted Cerebrus so far. The group also includes Samsung Electronics Co. Ltd.’s semiconductor foundry business, Cadence said. Samsung is the world’s largest maker of memory chips. 

Photo: Cadence