The Hybrid Memory Cube consortium, a group backed by more than 100 tech companies including the three largest memory makers in the world, has announced the final specifications for its three-dimensional DRAM technology after 17 months of development. The aim of the new technology is to support a new kind of computer chip that merges processing power and memory into a dense cube structure capable of packing more memory whilst reducing power consumption.

The Hybrid Memory Cube is the brainchild of industry giants including Hynix, Micron and Samsung, whose prototypes have hit an impressive throughput speed of around 128GB/s, which is roughly ten times faster than today’s standard DDR3 memory.

The technology is built on something called through-silicon vias, or TSVs, which allows silicon layers to be stacked one atop of the other and interconnected via conductive channels, or ‘vias’ that join each layer of silicon together. This allows for a new, super-dense design that incorporates dozens more memory modules into the footprint of a single module, while at the same time offering shorter signal paths between layers. In its tests, Micron was able to demonstrate peak data throughput up to ten times faster than that of regular two-dimensional memory constructs, whilst achieving an incredible 70% more power efficiency and reducing the size of memory modules by 90%. For a more detailed view of the Hybrid Memory Cube, check out the official specifications here (PDF).

Hybrid Memory Cube should help to solve one of the biggest problems facing the computing industry today. Whilst chip makers have been doing sterling work in making ever-faster CPUs, they’ve struggled to make memory chips that can keep up with them. Basically, while our CPUs are lightning fast, the chips cannot feed them with information quickly enough to make the most of this new power, meaning that processors are left standing idle while waiting for information to reach them. This leads to wasted energy and a reduction in the computer’s overall performance, something that’s becoming more pronounced as technology improves.

“The achieved specification provides an advanced, short-reach (SR) and ultra short-reach (USR) interconnection across physical layers (PHYs) for applications requiring tightly coupled or close-proximity memory support for FPGAs, ASICs and ASSPs, such as high-performance networking, and test and measurement,” says the consortium in its press release.

“The next goal for the consortium is to further advance standards designed to increase data rate speeds for SR from 10, 12.5 and 15Gb/s up to 28Gb/s. Speeds for USR interconnections will be driven from 10 up to 15Gb/s. The next level of specification is projected to gain consortium agreement by the first quarter of 2014.”

We’re still waiting on development of the chips themselves, but once they’re ready – possibly even later this year – these will be able to improve speed of high-performance computing, networking and gaming applications by up to 15 times present capabilities, and perhaps even faster over time. In other words, blazing fast.