Intel Corp. has upset IT’s applecart by announcing a big change to its chip development plans. As it announced its second quarter results, the company confirmed it’s planning to build a third generation of 14nm chips, shelving plans to switch to a 10nm process until the second half of 2017.

The move illustrates the difficulty Intel and other chip makers face in keeping up with “Moore’s Law”, and could spell the end to Intel’s “tick-tock” strategy that alternates manufacturing process shrinks—”ticks”—with major microarchitectural improvements—”tocks”. Each new process size generally brings increased performance and lower power consumption, while each new microarchitecture is supposed to bring improvements and new features to the processor cores. As such, the decision to break this cycle will have a big impact on data centers and IT in general over the next couple of years.

Intel has been operating its staggered release “tick-tock” strategy since 2007. Its current generation of chips, the Broadwell processors, are a “tick” because they’re the first batch to be built on a 14nm process. The next generation Skylake processors (to be released later this year) are a “tock”, as these are also built using the 14nm process, but come with significant architectural improvements.

Skylake was originally supposed to be succeeded by Cannonlake, the next “tick” in its strategy. These chips were to be built using the 10nm process, but yesterday Intel’s CEO Brian Krzanich said this would no longer happen. He told shareholders the migration to 14nm was more difficult than first anticipated, and this followed previous difficulties in migrating to the 22nm process.

As such, Intel now anticipates the transition to a 10nm process won’t be any easier, and so it’s giving itself more time to pull it off. In the interim, Intel now says it will produce a third 14nm chip, Kaby Lake, details of which were leaked last month, though little is known of its capabilities.

“Tick-tick-tock”?

The break in the “tick-tock” cycle is embarrassing for Intel, and it could have wider implications for the IT industry. That’s because the industry designs its purchasing and deployment plans to work in tandem with Intel’s “tick-tock” release schedule. Now there’s a hiccup all of a sudden, and that could cause headaches for anyone who was planning to build out their data centers next year with new machines powered by the faster 10nm chips.

Still, Krzanich told shareholders that the decision to delay 10nm is the correct one, at least for now. He also said the company should be able to resume its “tick-tock” cycle in the near future.

“Our customers said, ‘Look, we really want you to be predictable. That’s as important as getting to that leading edge’,” said Krzanich in Wednesday’s earnings call. “We chose to actually just go ahead and insert – since nothing else had changed – insert this third wave [with Kaby Lake]. When we go from 10-nanometer to 7-nanometer, it will be another set of parameters that we’ll reevaluate this.”

Intel’s change of plans underlines just how difficult it is for chip makers to keep up with Moore’s Law. Coined ex-Intel chairman Gordon Moore in the 1960s, Moore’s Law argues that the number of components on a chip would double every couple of years.

While chip makers have been able to keep to that prediction up until today, the process of shrinking microprocessor components has become increasingly difficult. Future processes demand complex manufacturing techniques and exotic technology that just doesn’t exist right now, at least not in a form that makes widescale production possible.

IBM Research recently unveiled its first prototypes of a 7nm chip, but the commercial viability of this process is still unproven and it’s not clear when they’ll come to market. As such, the IT world had better brace itself for more delays of this kind in the future.

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