Synopsys Inc. today introduced a suite of hardware designs that chipmakers can use to integrate the PCIe 7.0 interconnect technology into their products.

According to the company, the suite is the industry’s “first complete” blueprint collection with all the core components necessary to implement PCIe 7.0. It comprises four main elements: a controller, PHY designs, a cybersecurity module and hardware verification technology.

PCIe is an interconnect for linking a computer’s internal components with one another. The technology is used for, among other tasks, attaching graphics cards to data center servers. PCIe also lends itself to integrating other components into servers, notably flash storage, and is also widely used in the personal computer market.

PCIe 7.0 is an upcoming iteration of the technology set to release next year. Compared with its predecessor, the new specification can transfer data between a computer’s components twice as fast. This speed boost will help improve the performance of artificial intelligence applications that use PCIe-powered components such as graphics processing units.

Sunnyvale, California-based Synopsys is one of the largest providers of electronic design automation applications, the software that chip engineers use to design processors. The company also provides prepackaged chip blueprints that semiconductor teams can use to speed up their work. The new PCIe 7.0 blueprint bundle that Synopsys debuted today is the latest addition to this portfolio of prepackaged designs.

The bundle’s first component is a set of technical assets for implementing a PCIe controller. This is a tiny chip tasked with coordinating how data flows over the PCIe link that connects two computer parts. The controller is provided alongside PHY components, which carry out the low-level tasks involved in turning data into a form that can be sent over a PCIe link. 

In PCIe links, the controller and PHY layer use a technology called PAM4 to transmit information. PAM4 encodes data into electric pulses, with the voltages of those pulses representing different combinations of ones and zeros. In parallel, the underlying hardware also performs a number of other tasks, such as filtering any errors that may have found their way into the data while it traveled across the PCIe link.

The new controller and PHY designs are up to 50% more power-efficient than previous-generation PCIe implementations, according to the company. This means that servers equipped with the technology can move data between their internal components using less electricity, which lowers operating costs.

Synopsys’ PCIe 7.0 bundle also includes a version of the company’s IDE, or integrity and data encryption, module. It’s a component designed to make the data sent over a PCIe link inaccessible for any hackers who may obtain physical access to the host device.

Synopsys’ IDE encrypts information to make it unreadable. According to the company, the module also helps mitigate the risk of replay attacks. Those are cyberattacks in which hackers gain access to a computer’s PCIe link, intercept sensitive pieces of data that are sent over this link and temper with them.

The fourth component of Synopsys’ PCIe 7.0 bundle is a set of technologies for performing hardware validation. That’s the task of checking chip designs for flaws before manufacturing. According to Synopsys, its verification toolkit can make it easier to integrate its new PCIe offering into semiconductor products and will thereby simplify product development for customers.

“Accelerating every interconnect within the data center, including PCI Express, is critical to address the performance demands of AI clusters at scale,” said Debendra Das Sharma, senior fellow and chief I/O architect at Intel Corp. “The combination of Synopsys IP for PCIe 7.0 and Intel’s future generation products will offer system architects both the bandwidth needed for the most demanding data center workloads and seamless ecosystem integration.”

PCIe 7.0 is bidirectional, which means that a chip such as GPU can send data to the server into which it’s integrated and receive data at the same time. Data center graphics cards typically have 16 PCIe lanes, physical interconnect links for transmitting information. Synopsys says PCIe interconnects based on its newly detailed blueprint bundle can provide up to 512 gigabytes of bidirectional bandwidth per second in a 16-lane configuration.

Photo: Synopsys