Artificial intelligence chiplet startup TYLsemi Inc. revealed itself to the world today, announcing it has raised $43 million in early-stage funding to disrupt the semiconductor industry and transform the way companies design and develop custom AI accelerators.

Today’s round was led by Matter Venture Partners and saw participation from Viola Ventures, GHOVC, Egisten and a number of strategic investors from within the semiconductor industry.

The startup is on a mission to make custom semiconductor design more feasible by helping companies to get around the cost, complexity and the physical limitations of building advanced AI chipsets. As AI workloads become more prevalent, many organizations have realized that they’re approaching the physical limits of what traditional monolithic chips are capable of. Those processors are printed on a single silicon wafer, which means squeezing everything from the transistors to the connectivity and power delivery mechanisms onto the same substrate.

To get around this, many bigger organizations have developed customized application-specific integrated circuits known as XPUs, which are geared towards specific workloads to enhance their performance. Some of the best known XPUs include Google LLC’s tensor processing units and Amazon Web Services Inc.’s Trainium chips. But the costs of designing and building XPUs have always been immense, running into hundreds of millions of dollars.

TYLsemi wants to change this and make XPU design more accessible with an alternative path. By combining standards-based and production-ready chiplets with custom design, packaging and supply-chain ownership, it believes it can reduce the costs of custom AI silicon development by almost 50%, and get it done in less than half the time. TYLsemi’s approach is already proving itself, with the startup securing engagements with a number of tier-one customers.

The use of chiplets is central to TYLsemi’s strategy. Instead of squeezing everything onto a single chip, chiplets are smaller, specialized and modular dies that perform distinct functions, such as processing, memory or power management. These modular components can then be integrated into a single 3D package that acts as a unified, high-performance system. With this approach, TYLsemi not only bypasses the limitations of monolithic designs, but dramatically simplifies the chip design process.

Democratizing chiplet design

Co-founder and Chief Executive Mohit Gupta (pictured) told SiliconANGLE that the market for AI accelerators is forecast to hit $604 billion annually by 2033, and custom silicon XPUs are expected to be the fastest-growing segment within it. “At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio,” he said.

This is where TYLsemi hopes to change things. Until recently, only the biggest merchant chip vendors and hyperscale data center operators have had the resources to develop custom AI silicon, Gupta said. He added that alternatives such as EDA Vendors, IP providers and design services firms only provide part of the solution. “None of them can deliver production-ready, standards-based chiplet silicon with integrated packaging, validation and supply chain ownership, which means customers have to manage the integration risks themselves,” Gupta said.

According to Gupta, TYLsemi changes what’s possible as a result of recent advances in 2.5D and 3D packaging technologies, which make it possible to integrate heterogeneous dies and dynamic random-access memory into a single system for the first time. “This, plus the emergence of standardized interconnects such as UCIe, means chiplet design is now practical and scalable for anyone,” he promised.

Gupta said the company has a number of production-ready chiplets that are ready for customers to use, either as standalone components or the building blocks for full custom silicon architectures. These include TYL.IO, which is a family of input/output connectivity chiplets designed to enable high-bandwidth communication across chip systems. It supports the PCIe, ESUN, and UALink data transfer protocols, and the company’s future roadmap calls for the integration of co-packaged silicon photonics that seem destined to enable the rack-scale networks of the future.

In order to handle that efficiency, the company has built TYL.Power, which is a packaged power delivery system that relies on an integrated voltage regulator chiplet to maximize energy efficiency. There’s also TYL.Mem, a versatile memory connectivity chiplet that’s currently under development. Finally, there’s TYL.Forge, which is an end-to-end platform that integrates both custom compute and fabric chiplets. It’s designed as a full-stack offering that encompasses intellectual property, foundry management, advanced packaging and production-readiness into a single cohesive system.

“Customers can build on TYLsemi’s pre-validated, UCIe-based chiplets either as standalone components or combined into a full custom silicon program through TYL.Forge, rather than developing die-to-die connectivity, power delivery, and integration from scratch each time,” Gupta said. “The main compute or fabric die is where customers focus their differentiation, while leveraging other chiplets as components to build out the system. Because the underlying chiplets are standards-based rather than proprietary, customers aren’t locked into a rigid TYLsemi architecture.” 

Gupta said the promised 50%+ cost efficiencies his company claims come from reusing proven, pre-validated building blocks and packaging expertise, so there’s no cutting corners in terms of performance. “We saw this with Meta, which recently shared how it was able to use a chiplet-based platform to build four distinct XPU designs, each optimized for a specific workload,” he pointed out. “It did this in just two years. That would have taken at least four years with a traditional, monolithic approach.”

Industry expertise

Gupta and his co-founder Sunil Bhardwaj have plenty of expertise when it comes to designing chiplets, having previously served as executives of Alphawave IP Group Plc, a British startup acquired by Qualcomm Inc. for about $2.4 billion last summer. Alphawave designed and built specialized interconnects that link together multiple compute modules into a single system-on-chip. Prior to working at Alphawave, the co-founders were senior engineers at companies including the RISC-V-based chip design startup SiFive Inc. and Cadence Design Systems Inc., which sells semiconductor design software.

With the funding from today’s round, TYLsemi says it’s going to provide samples of its TYL.IO and TYL.Power chiplets to qualified customers next year in partnership with Taiwan Semiconductor Manufacturing Co. It’s also engaged with a number of early partners through the TYL.Forge platform.

Zvika Orron of Viola Ventures said TYLsemi is democratizing access to custom silicon development, so instead of XPUs being a competitive moat reserved for only the biggest hyperscalers, they’ll be accessible to any company. “It has built the chiplet platform that the entire AI silicon industry desperately needs,” he said. “It can serve the scale of hyperscalers and the speed requirements of much smaller, emerging AI companies in the same breath.”

Matter Venture Partners’ Wen Hsieh said TYLsemi’s ability to speed up advanced silicon development and make it more cost-efficient will provide a defining advantage to AI companies. “It’s building foundational chiplet technologies for custom silicon that will make the design process faster, less risky, and more accessible, unlocking significant value and velocity across the AI ecosystem,” he promised.

Images: TYLsemi