Intel Corp. has shared new information about some of the emerging technologies that it’s developing to facilitate the creation of faster, more efficient processors.

Scientists from the company’s components research group detailed the technologies on Saturday at the IEDM 2021 semiconductor event. Intel said the innovations are part of its effort to continue the “advancement and benefits of Moore’s Law well beyond 2025.”

To build better processors, chipmakers such as Intel are developing ways to reduce the amount of space that their transistors take up. The less space transistors require, the more of them can be placed on a processor, which leads to increased performance — the essence behind Moore’s Law, an observation that the number doubles every couple of years.

One way chipmakers reduce space requirements is by shrinking the individual transistors in a processor. But that’s not the only way to go about the task.

On today’s processors, transistors are arranged next to each other in a two-dimensional configuration. At IEDM 2021, Intel detailed its work on a chip design technique that could reduce space requirements by allowing for transistors to be placed atop one another instead of side by side. According to Intel, the technique has the potential to facilitate a 30% to 50% area improvement for transistor scaling, which may enable the creation of faster chips.

Another focus of Intel’s development roadmap is a technology called Foveros. The technology provides the ability to create processors that are each composed of multiple smaller chips stacked atop one another. Similarly to how placing transistors atop one another can increase performance, stacking chips also makes it possible to improve processing times.

The effectiveness of chip stacking depends in significant measure on the interconnect used to link together processors. The faster the interconnect, the faster data can travel between processors. Reducing the time it takes data to arrive at its destination allows processing to begin sooner, which boosts performance. 

Intel’s Foveros technology links stacked chips together using an array of tiny connectors located a few dozen microns apart. A micron equals one millionth of a meter. Intel’s engineers are working to improve chip connectivity by shortening the distance between individual Foveros connectors from a few dozen microns to less than 10. 

Such a distance reduction would make it possible to increase significantly the number of connectors that can be placed in a given area, Intel says. The company is aiming to achieve a more than tenfold increase in density, which could lead to better chip performance.  

Intel’s components research group is developing a large number of new technologies in parallel. Another project that the group detailed at IEDM 2021 focuses on using gallium nitride to build some of the power management components found in modern chips. Gallium nitride is a material that can manipulate electricity more efficiently than traditional silicon in certain respects, which could make it useful for chipmakers such as Intel. 

Image: Intel