Integrated circuit and electronic hardware design company Cadence Design Systems Inc. today announced the release of an artificial intelligence “Super Agent” designed to transform front-end silicon design and verification.

The company said Cadence ChipStack AI Super Agent will help revolutionize how engineers automate chip design by improving productivity and speeding up coding, design and testbench creation by a factor of 10, as well as creating test plans, orchestrating regression tests, debugging and automatically fixing issues.

In an interview with SiliconANGLE, Matt Graham, senior group director, verification software product management, and Kartik Hegde, senior group director of agentic AI, explained that the new agent focuses on the increasingly problematic pain point of verification in chip design. The Super Agent’s name, ChipStack, is a product name carryover from when Cadence acquired the company in November 2025.

“The ChipStack AI Super Agent is an umbrella, or symphony of agents, like an IP design agent, a verification agent, a system-on-chip integration agent, a debugging agent and more, working together,” explained Graham.

Verification is the bottleneck for engineers. ChipStack is intended to act as a junior engineer in the face of increasing complexity. “Verification is fundamentally NP complete and grows exponentially,” Graham said. “Double the gate count, square the state space. That’s the fundamental equation.”

Inside the agentic core, the mind-in-the-machine, Cadence developed the system to develop a “mental model” that could hold the entire project for engineering teams so that it could interpret all artifacts at once and act like a junior engineer. This allows chip design engineers to input the documentation, block diagrams, waveforms and timing relationships into the agentic loop, have it verified and then ask questions before sending it to automation down the line.

Graham framed this problem within the chipmaking industry as having millions of dollars on the line. A single flaw could cost significant amounts if it went into production. Therefore, it needs to be caught early, so testing takes a significant number of resources.

Putting AI to work in chip design and verification

The agentic AI system integrates directly with Cadence’s optimization AI and AI assistant solutions, which have already been used in more than 1,000 tapeouts to date, including within the company’s Cerebrus Intelligent Chip Explorer, as well as JedAI data and AI platform.

In an example workflow, a verification engineer takes the agentic system and points it at specifications, the various documents of chip design, drawings, pinouts and so forth and it generates the mental model. Then it generates a test plan, writes and updates test benches, runs simulations, reads logs/waveforms, identifies root causes and proposes fixes.

At each stage, the engineer remains in the loop, working alongside it like a senior engineer proposing direction with a junior engineer, the agent, executing actions.

“Verification is a deeply natural language reasoning problem and large language models are natural language processing engines,” Hegde said. “It’s just a perfect fit for the hair-on-fire problem the industry has.”

Ideally, Cadence wants to build toward a fully autonomous solution that will be able to send out agents and take a prompt, design a chip and do the testing, then provide a fully working chip.

“The moonshot is fully autonomous integrated chip design,” Graham said, “but we’re taking the first steps.”

As for enterprise readiness, Cadence said the product is available to deploy in the cloud, hybrid and on-premises. Many chip design and fabrication companies are extremely covetous about their intellectual property and do not want it leaked to third parties.

Cadence’s ChipStack AI Super Agent is currently in early deployment with several chip design and system companies, including Altera Corp., Nvidia Corp. and Tenstorrent Inc.

Images: SiliconANGLE/Microsoft Designer; Cadence Design Systems