IBM Research today heralded what it’s calling a “breakthrough” in compute memory architecture that can achieve a superior performance for artificial intelligence computing workloads in hybrid cloud platforms.

The researchers have created what they claim is the first embedded Magnetoresistive Random-Access Memory technology built on a 14-nanometer architecture that it calls Spin Transfer Torque MRAM, or STT-MRAM. The new architecture helps to solve a crucial memory bottleneck in data-intensive hybrid cloud and AI workloads.

IBM said in a blog post that as enterprises move their most demanding workloads to hybrid cloud platforms they face a problem known as the “compute memory bottleneck.” That’s a memory shortage that results from the processors in those systems being much faster than existing memory systems.

IBM said its new STT-MRAM architecture, presented at the IEEE International Electron Devices Meeting conference this week, can solve this bottleneck between memory and processors because it enables faster memory performance.

STT-MRAM works by using electron spin to store data in magnetic domains, and combines the high speed of Static RAM with the higher density of traditional DRAM to provide a more reliable memory architecture. IBM said that by deploying STT-MRAM in last-level CPU cache, it helps reduce the amount of reading and writing to memory that’s required in data-intensive workloads, thereby reducing system latency and power consumption while increasing bandwidth.

IBM said the 14-nanometer Embedded STT-MRAM CMOS technology, described in a white paper published today, is the most advanced MRAM system ever built. IBM said it will allow for a “much more efficient, higher-performing system” for AI workloads in hybrid clouds.

The new architecture is enabled by the use of some advanced magnetic materials that are detailed in a second paper. The use of these materials enables greater density in STT-MRAM systems that can store twice as many bits, leading to a significant increase in data retrieval performance, IBM said.

IBM also provided an update on its research into “analog in-memory computing,” where compute and memory are combined into a single device for more demanding AI workloads. This specialized hardware has the potential to train increasingly complex AI models with far greater energy efficiency, IBM said.

One of the challenges in creating specialized analog in-memory compute hardware for AI is known as the “synaptic weight mapping problem.” Synaptic weights are used to indicate the strength of a connection between two nodes in a neural network, and they need to be accurately mapped onto analog nonvolatile memory devices to enable deep learning inference. But doing so is a considerable challenge, IBM said.

IBM’s paper, “Precision of Synaptic Weights Programmed in Phase-Change Memory Devices for Deep Learning Inference,” discusses how analog resistance-based memory devices that rely on pulse-code modulation might address the mapping challenge. It describes a way to map the synaptic weights accurately, both analytically and through array-level experiments.

A second paper on analog AI, “Unassisted True Analog Neural Network Training Chip,” describes IBM’s concept of an analog neural network chip. It’s essentially a “resistive processing unit” or RPU, and IBM says it can achieve superior performance to comparable digital systems in real-time, thereby achieving the promised “analog advantage” in AI inference.

Photo: George Rex/Flickr