Semiconductor startup Eliyan Corp. today announced that it has reached first silicon, meaning its chip technology was successfully manufactured at a fabrication facility.

Eliyan used Taiwan Semiconductor Manufacturing Co. Ltd.’s five-nanometer manufacturing process. Reaching first silicon is a major milestone for chip startups that marks an important step toward mass production. For Eliyan, the milestone comes less than a year after it raised $40 million in funding to support commercialization efforts.

Santa Clara, California-based Eliyan develops an interconnect technology for linking together chiplets. The startup that its technology can help semiconductor companies develop faster, more cost-efficient processors.

The traditional approach to chip manufacturing is to produce each processor as a single piece of silicon. All the processor’s compute and memory circuits, as well as its various supporting components, are implemented on one die. In recent years, chipmakers have started moving away from that approach to a newer technology known as the chiplet architecture.

A chiplet-based processor is not built from a single die. Rather, its components are each implemented on separate pieces of silicon that are linked together after manufacturing. Those pieces of silicon, or chiplets, are linked together using a technology known as an interconnect.

Eliyan offers an interconnect product called the NuLink PHY. That’s the product with which the company has achieved first silicon using TSMC’s five-nanometer process. According to the Eliyan, NuLink PHY is more scalable and cost-efficient than interposers, a type of interconnect that is in wide use today.

An interposer is a flat, rectangular piece of silicon that functions as a processor’s base layer. The chiplets that comprise the processor are placed atop this base layer. Under the hood, the interposer contains tiny wires that allow chiplets to exchange data with one another for processing purposes.

Some interposers also contain additional components. So-called active interposers include not only wires that facilitate the movement of data between chiplets, but also transistors. Those transistors optimize the flow of data between chiplets to improve performance. 

Interposers allow a processor’s chiplets to rapidly exchange data with one another, but have a number of technical limitations. Eliyan says its technology addresses those limitations.

When a processor is implemented atop an interposer, the interposer’s surface area becomes a major consideration. If an interposer measures two square inches, then only two square inches’ worth of transistors can be placed on top. That means chipmakers have to limit the number of transistors in their processor designs, which limits performance.

Eliyan says its NuLink PHY technology allows chipmakers to create larger processors than is possible with interposers. Moreover, it promises to reduce production costs in the process.

Interposers not only limit the size of processors but, because they’re complicated to manufacture, also increase production costs. There’s also an increased risk of manufacturing faults. The more complex a chip design, the more difficult it is to manufacture it reliably in large volumes. 

Eliyan claims that NuLink PHY not only avoids those issues, but also delivers similar performance and power efficiency as other advanced interconnect technologies. An interconnect’s performance is measured in terms of the amount of data it can transport between a processor’s chiplets. According to Eliyan, NuLink PHY provides 2.2 terabits per second of bandwidth per square millimeter.

“First silicon with the results and time frame we have achieved is a significant milestone and differentiator in the successful commercialization of our technology,” said Chief Executive Officer Ramin Farjadrad. “It positions us as the front runner in enabling the most efficient chiplet interconnect in the semiconductor industry.”

Going forward, Eliyan plans to enhance its chip technology so that it may be produced using additional manufacturing processes and fabs. The company is also working on an industry standard for interconnects optimized to manage memory traffic. That’s the data traffic between a processor’s compute circuits and onboard memory. 

Photo: Unsplash