Efficient Compute Corp. Inc. launched today with a new central processing unit that it claims is up to 100 times more energy-efficient than leading general-purpose CPUs.

The company also said it raised a $16 million seed funding round led by Eclipse Ventures LLC.

Efficient Compute’s Fabric architecture technology is based on foundational research conducted at Carnegie Mellon University and documented in a set of papers on its website. The technical details require an advanced degree in computer science to understand, but the core principles come down to eliminating much of the energy-consuming overhead of general-purpose CPU operations.

“CPUs have been optimized for performance first, often at the detriment of energy efficiency,” said Brandon Lucia, co-founder and chief executive of Efficient Computer and a CMU electrical and computer engineering professor, told SiliconANGLE. “They spend a lot of time with that instructions for memory figuring out how many operations they can run at the same time.” That enhances performance but at the expense of power consumption.

Efficient’s architecture eliminates much of that overhead by moving decisions about parallel processing to its purpose-built compiler and using spatial parallelism. That’s a method of executing different instructions at the same physical time but in different locations on the processor.

It also uses a simple onboard network to connect parallel processing elements that’s “about as efficient as it’s possible to be,” Lucia said. “It’s essentially just wires connecting two points in a range of parallel processing elements. It doesn’t get much more efficient than that.” The design makes the chipset somewhat larger than a standard CPU but with comparable performance thanks to optimized compilation.

Compiler ‘secret sauce’

The compiler is critical to the design’s energy efficiency. Lucia said it can ingest C, C++, Tensorflow and some Rust applications using Multi-Level Intermediate Representation, a unified software framework for compiler development. That enables many existing applications to run on the Fabric architecture without modification.

“It’s in the interest of anyone who makes a language or a framework for machine learning, signal processing or whatever to make a little adaptation layer that goes from their front end into MLIR,” Lucia said. “We benefit from that basically for free.”

The compiler creates an intermediate representation of a program that models the structure of the underlying hardware. “We have a series of steps called lowering, where we move the representation closer and closer to what is physically implemented in the chip,” he said. “Along the way, we restructure the data flow graph representation of the program to further reduce the amount of energy it consumes once we map it onto the fabric.”

Lucia said target markets include industrial internet of things devices, infrastructure monitoring and wearables. He said many of the limitations of current devices are the result of power consumption issues requiring frequent round-trips to the cloud or precluding smart device use altogether.

“If you could scale deployments with smart devices, you could do so much more with machine learning at the edge,” he said. “A lot of industrial infrastructure monitoring currently doesn’t make sense because you need to swap batteries every few months. You can go from months to years of battery time.”

The chipset is currently in “tape-out,” a design term that marks the completion of design and the start of manufacturing. Efficient Compute has contracts with application vendors it wouldn’t name and expects to ship production versions to customers in early 2025.

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