British chipmaker Arm Ltd. today said it’s adding an “Arm Custom Instructions” feature set to its latest Armv8-M architecture.

The idea is to give customers a way to add special instructions for specific embedded and “internet of things” applications to its central processing units. The Armv8-M architecture is the basis of Arm’s current family of M33 Cortex-M low-powered processors (below), which are used in a range of IoT and mobile devices.

Arm’s business model is notably different from other chipmakers in that it licenses the designs of its chips to partners, which then build the actual hardware themselves. Many of those partners want to adapt Arm’s designs so they can build processors that are specialized at particular tasks, offering increased performance and more efficiency.

Arm said today at its 15th annual Arm TechCon 2019 conference that Custom Instructions are based on the notion that the CPU is a chassis for Arm silicon partner innovation. “There’s scope for adding flexibility within the chips,” Arm Chief Executive Simon Segars (pictured) said in his conference keynote this morning, such as adding compute or security capabilities that aren’t needed for every broad workload.

Arm Custom Instructions give chip designers a way to add “custom datapath extensions” to its M33 Cortex-M CPUs. With this, they can create various kinds of accelerators that translate to better performance in edge computing use cases such as artificial intelligence, machine learning and self-driving cars, the company said.

“Arm’s custom instructions can help solve chipmaker issues of adding acceleration with low latency, without requiring an acceleration card,” said Patrick Moorhead, president and principal analyst at Moor Insights & Strategy. “It’s a novel approach because it supports ‘bring your own instructions,’ meaning chipmakers can add their own intellectual property in a structured manner. This doesn’t replace higher-end accelerator chips.”

Indeed, Segars reemphasized in his keynote address this morning Arm’s goal to have Arm chips span the entire range of computing needs, especially as 5G network, the “internet of things” and artificial intelligence all mature simultaneously. “We want to span entire continuum, from biggest computers to smallest sensors,” he said.

Arm said its custom instructions feature will be implemented in its M33 CPUs in the first half of next year at no additional cost to licensees.

Also at Arm TechCon, the company said it’s introducing a new governance model for its popular Mbed operating system for low-powered IoT devices. Mbed OS includes all the features developers need to build a connected product based on an Arm Cortex-M microcontroller, including security, connectivity, an RTOS and drivers for sensors and I/O devices.

The company said it’s introducing the Mbed OS Partner Governance model to give users more of a say in the future development of the operating system, with the goal of increasing innovation. The new model will see the creation of a Product Working Group which will get together once a month to vote on which new Mbed OS features should be given priority. The meetings are open to all members of the Mbed Silicon Partner Program, Arm said.

“While Mbed OS has always been an open-source IoT operating system, we are shifting its governance so that our silicon partners can directly influence future development and enhance our efforts in building out new capabilities, features and functionality, which are critical in scaling to a trillion connected devices,” the company said.

Elsewhere at TechCon, Arm announced a new “Autonomous Vehicle Computing Consortium” in partnership with the likes of Robert Bosch GmbH, Continental AG, Denso Corp., General Motors Co., Nvidia Corp., NXP Semiconductors and Toyota Motor Corp.

The goal of the consortium is to try to overcome some of the biggest challenges in the way of creating fully autonomous, self-driving vehicles. One of its first tasks will be to come up with “a set of recommendations for a system architecture and computing platform that reconciles the performance requirements of autonomous systems with vehicle-specific requirements and limitations.”

With reporting from Robert Hof

Photo: Robert Hof/SiliconANGLE; image: Arm