Intel expands 10-nanometer chip lineup with power-efficient Tremont processors
Tremont is aimed at low-power systems that prioritize efficiency over performance. Intel sees hardware partners including chips from the series in mobile devices, “internet of things” gadgets and certain data center hardware such as networking systems.
One of the first products that will ship with Tremont silicon is the Surface Neo, the dual-screen Windows tablet Microsoft Corp. unveiled a few weeks ago. Intel claims the new CPUs bring major improvements over the previous-generation Goldmont Plus processor family they will succeed. Tremont chips provide up to 30% better single thread-performance, according to the company, as well as higher power efficiency.
Some of the performance gains come from the upgraded branch prediction mechanism that Intel has built into the series. Branch prediction is a technique wherein a processor looks at the possible outcomes of an operation, guesses the most likely result and performs a part of the calculation in advance. That preparation allows tasks to be carried out faster.
Another notable feature in Tremont is support for Intel’s Foveros technology. Foveros allows several types of chips to be combined on a single die, which makes it possible to mix-and-match components into highly specialized processors. Microsoft’s Neo tablet combines Tremont silicon with processing cores based on Intel’s more performance-oriented Ice Lake architecture.
“Tremont is Intel’s most advanced low-power x86 architecture to date,” said Stephen Robinson, the chief architect for the new series. “We focused on a range of modern, complex workloads, while considering networking, client, browser and battery so that we could raise performance efficiently across the board.”
Tremont is entering a tough market. The processor designs of Intel rival Arm Ltd. dominate the mobile segment and can be found in many millions of other low-powered systems as well, from smart home appliances to drones. Arm earlier this week unveiled a new collection of mobile chips including two neural processing units specifically optimized to run machine learning models.
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