Several major chipmakers today announced they’re teaming up to create an industry standard for chiplet technology, an important component of many modern processors. 

The companies participating in the initiative include ASE Inc., Advanced Micro Devices Inc., Arm Ltd., Intel Corp., Qualcomm Inc., Samsung Electronics Co. Ltd. and TSMC Ltd. They’re joined by Microsoft Corp., Facebook parent Meta Platforms Inc. and Google LLC’s cloud business.

The companies’ goal is to develop an industry standard for building processors that use chiplet technology. A chiplet is an integrated circuit optimized for a specific task, such as running artificial intelligence models. Multiple such integrated circuits can be linked together to form a single processor.

Many of the most advanced processors on the market today are made using chiplet technology. AMD’s flagship Ryzen central processing units, for example, each comprise multiple chiplets. Intel, meanwhile, is using the technology as the basis of Ponte Vecchio, a data center chip with 100 billion transistors that’s optimized to run AI workloads.

A collection of chiplets can’t simply be soldered together to form a working processor. Rather, they have to be linked together in a way that allows data to travel between the individual chiplets for processing. This is the requirement that Intel and AMD aim to address using the new industry standard they’re developing with other major tech firms.

The industry standard the companies are developing is known as UCIe. It aims to provide a set of common technical best practices for developing technology that allows chiplets to be linked together into a single processor. This technology is commonly known as an interconnect. 

Having a common set of best practices simplifies product development for chipmakers by allowing them to draw on technical lessons gleaned by other market players. The result is that chipmakers can bring new products to market faster. 

There is also another, potentially equally significant benefit for the industry. In theory, future chiplets that will be compatible with the newly announced UCIe standard could be linked together to form a single processor even if they are made by different companies. That could create opportunities to develop new kinds of processors that combine technologies from several different chipmakers.

The newly announced UCIe chiplet standard specifies a set of requirements that should be met when linking together chiplets in a processor. The requirements address technical details such as the manner in which electric signals travel between different parts of a processor. The standard also covers other areas, such as ways that chipmakers can test their silicon to ensure that it’s compatible with UCIe. 

“Integrating multiple chiplets in a package to deliver product innovation across market segments is the future of the semiconductor industry and a pillar of Intel’s IDM 2.0 strategy,” stated Sandra Rivera, executive vice president and general manager of Intel’s Data Center & AI business.

UCIe enables chipmakers to create the hardware mechanism, or interconnect, that links together the chiplets in a processor from multiple materials. According to AnandTech, chipmakers can use both silicon-based technologies and other approaches. UCIe is expected to facilitate the creation of interconnects that can move 1.3 terabits of data per second per millimeter across chiplets.

The standard also specifies the protocol, or set of procedures, that will be used to manage chiplet-to-chiplet data transfer. The basis of the protocol will be an existing technology called PCIe that is already widely used in data centers. Moreover, the companies participating in the effort plan to develop software and tools to help chipmakers ensure their products comply with the standard. 

“Microsoft is joining the UCIe industry organization to accelerate the pace of datacenter innovation and enable new breakthroughs in silicon design,” said Microsoft Distinguished Engineer Leendert van Doorn. “We look forward to combining efforts of the organization with our own achievements to drive step-function improvements in silicon architecture for the benefit of our customers.”

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