Networking chip company Astera Labs Inc. is trying to ease the traffic congestion in artificial intelligence data centers with the launch of the latest generation of its Scorpio smart data fabric switch family, the X-series.

According to the company, it’s the largest open and “memory-semantic” fabric switch in the industry, designed to help hyperscale data center operators scale up their compute capacity while avoiding latency issues.

The new switch is being launched alongside an expanded Scorpio P-Series PCIe Fabric Switch family, which now comes in configurations ranging from 32 lanes to 320 lanes. It says it’s giving data center architects more flexibility as they struggle to shuffle massive streams of data between clusters of AI processors.

Astera Labs says the new switches will play a vital role in scaling AI system. As the world’s leading large language models evolve into multitrillion-parameter behemoths, it’s no longer possible to squeeze them into a single server rack. The only way to run these kinds of models is to link hundreds or even thousands of graphics processing units into enormous clusters so they can work together as a single, giant computer.

This has become the standard way for AI data centers to operate, but it also causes immense congestion as data shuffles back and forth between those chips. It’s extremely inefficient, because when GPUs are waiting for data to arrive from another part of the cluster, it means they’re sitting idle. For AI clusters that are rented out at the cost of thousands of dollars per hour, that idle time is undesirable, to say the least.

Astera Labs’ Scorpio X-series 320-Lane Smart Fabric Switch is designed to solve this challenge by rethinking the way switches interact with the chips they’re linked to. Its novel memory-semantic architecture makes it possible for GPUs and other AI accelerators to access resources spread across the fabric using simple load/store operations, similar to how they might access data within their own local memory. The entire fabric becomes a single, unified memory pool, eliminating the overheads that arise from translating data packets in order to minimize latency.

The X-series switches can do this thanks to the company’s proprietary Hypercast and In-Network Compute technologies, which enable the switches to perform some data processing tasks itself. More specifically, it’s designed to handle “collective operations” such as data aggregation or distribution tasks. Because these no longer have to be done on the AI chip, they can be processed twice as fast – with a direct impact on the “token economics” of AI workloads.

Another key element of the X-series switches is their “high radix” design. Each chip boasts 320 lanes of PCIe 6 connectivity, which means they can be swapped for multiple legacy data center switches, reducing network complexity and the overall distance data has to travel.

Astera Labs says the older Scorpio P-series chips will now play a complementary role to the X-series family, with the new configurations designed to support “front-end network and AI compute system deployments.” With its support for open standards and platform-specific protocols such as NVLink Fusion and UALink, Astera Labs’ switches can provide the networking fabric for almost any kind of AI processor, it said.

Chief Executive Jitendra Mohan said chip connectivity bottlenecks must be avoided for the AI industry to continue scaling. “The frontier models driving today’s most demanding AI applications require connectivity infrastructure that keeps pace with the accelerators powering them,” he stressed.

Image: Astera Labs